Má jedinou vadu na kráse a to je "povadlý" displej viz foto. Na funkci nemá zásadní vliv, displej je čitelný. Jedná se o setrvalý stav už cca 2 roky, nezhoršuje se. Proto jsem to neřešil.
Dohoda na místě možná
Parametry:
Output level (0dBFS):
PCM: RCA single-ended output is 2V RMS, XLR balanced output is 4V RMS
DSD: RCA single-ended output is 1.8V RMS, XLR balanced output is 3.6V RMS
Output impedance: 22 ohms (RCA single ended) / 44 ohms (XLR balanced)
Frequency response: 20-20kHz +/-0.2dB
Signal to noise ratio: 125dB
Distortion characteristics:
THD+N (1kHz, 0dBFS) 0.00025% at fs=44.1Khz (PCM)
THD+N (1kHz, 0dBFS) 0.00030% at DSD256
Dynamic response (1kHz, -60dBFS) 125dB
Left and right channel separation >125dB
Balanced output noise floor: 2.2uv RMS
Amp balance maximum output power 3480mW@30Ω, 0dBFS
Load power
30Ω 3480mW
75Ω 1640mW
150Ω 920mW
300Ω 440mW
600Ω 220mW
Distortion of the amp balanced output, 0dBFS, fs=44.1Khz (PCM)
75Ω load THD+N -105dB
600Ω load THD+N -110dB
System compatibility:
1, Windows 7, Windows 8, Windows 10; 32/64 bit, need to install a dedicated driver
2, Native MacOS 10.6 and later, using the system comes with a driver
3, Native Linux with UAC2 compliant kernel, using the system's own driver, (tested on Ubuntu and Daphile systems, based on INTEL X86 platform)
4, Android OS 4.2 and above, the device needs to support OTG function, and the following 5.0 recommendations are used with a dedicated player.
The I2S interface is input using an HDMI socket:
1. LVDS differential signal with a level of 3.3V;
2. The I2S interface is compatible with multiple I2S output signal definitions, and the FPGA has built-in PCM/DSD signal automatic identification algorithm;
3. The DSD ON signal can also be defined by itself. The DSD ON signal can be input to the PIN13, 14, 15, and 16 pins of the socket.
4. The phase of PIN1-3 and PIN7-9 is adjustable, and the user can configure the phase of the two pairs of outputs through one switch.
Weight: 3.4kg
CD Přehrávače
